Create Buses with Variant Conditions

This example shows how to create bus signals with elements having different variant conditions. This model has two signals (‘a’, ‘b’) that are merged to create a bus signal. These two signals have different variant conditions, V==1 and W == 1.

The bus selector is fed by two signals having two different variant conditions (V==1 and W==1). When this bus signal is fed into a bus selector and when you select the individual signals from the bus, the variant condition is also selected.

To see the completed model, open theslexVariantBusmodel.

Variant Condition Propagation with Bus

AVariant Sourceblock can accept either virtual or nonvirtual bus inputs.

Consider this model.

Bus is created with variant conditions V = 1 and W = 1. When conditions V and W are propagated through the bus and when individual elements are selected from the bus, conditions are also selected.

Code Generation

You can generate code for the model. To do so, on theAppstab of toolstrip, clickEmbedded Coder, then on theC Codetab, clickBuild. For more information on configuring model to generate code, seePrepare Variant-Containing Model for Code Generation.

When generating code with preprocessor conditionals, the bus types and hierarchies of all bus inputs must be the same.

虚拟和Nonvirtual Bus Behavior

Virtual buses provide the simplest approach for using buses to reduce signal clutter in a block diagram. Nonvirtual buses support modeling components (such as S-functions orMATLAB Functionblocks) that require explicitly specified interfaces. There is no change in the propagation behavior of variant conditions when variant conditions are propagated through a virtual or nonvirtual bus.

生成的代码for a virtual bus is as shown below.

/* Block states (default storage)forsystem''*/ typedefstruct{#ifV == 1 real_TUnitDelay_1_DSTATE; /*'/Unit Delay'*/ #define D_WORK_EX_BUS_VAR_COND_VARIANT_EXISTS #endif /* V == 1 */ #ifW == 1 int32_TUnitDelay_2_DSTATE; /*'/Unit Delay'*/ #define D_WORK_EX_BUS_VAR_COND_VARIANT_EXISTS #endif /* W == 1 */ #ifndef D_WORK_EX_BUS_VAR_COND_VARIANT_EXISTS char_rt_unused; #endif } D_Work_ex_bus_var_cond;

生成的代码for a nonvirtual bus is as shown below.

/* Block states (default storage)forsystem''*/ typedefstruct{#ifV == 1 || W == 1 myBusUnitDelay_DSTATE; /*'/Unit Delay'*/ #define D_WORK_EX_BUS_VAR_COND_VARIANT_EXISTS #endif /* V == 1 || W == 1 */ #ifndef D_WORK_EX_BUS_VAR_COND_VARIANT_EXISTS char_rt_unused; #endif } D_Work_ex_bus_var_cond;

You must have an associated bus object in the bus, which provides properties that Simulink^®uses to validate the bus signal. For more information on bus objects, seeSpecify Bus Properties with Simulink.Bus Object Data Types. The bus object used in the bus is unconditional and it generates unguarded code as shown below.

类型定义struct{real_Ta; int32_Tb; } myBus;

Variant Bus with Model Block

Consider this model containing aModelblock.

This model has two signals (‘a’, ‘b’) which have different variant conditions, V==1 and V==2.

From theModelblock, the bus selector is fed two signals having two different variant conditions (V==1 and V==2). When you select the individual signals from the bus, the variant conditions are also selected.

Known Limitations