采用Simulink Templates for HDL Code Generation - MATLAB & Simulink - 金宝app,下载188bet金宝搏,金宝搏官方网站

采用金宝appTemplates for HDL Code Generation

HDL编码器™ model templates in Simulink^®为您提供针对HDL代码生成的模型的设计模式和最佳实践。您从HDL编码器模型模型之一创建的模型具有其配置参数，并为HDL代码生成设置了求解器设置。要配置HDL代码生成的现有模型，请使用HDLSETUP.

Create Model UsingHDL编码器Model Template

To model hardware for efficient HDL code generation, create a model using an HDL Coder model template.

打开Simulin金宝appk启动页面。在matlab中^®Home tab, select the金宝appbutton. Alternatively, at the command line, enter:
```
金宝app
```
在里面HDL编码器部分，您会看到针对HDL代码生成预配置的模板。选择模板在Simulink编辑器中打开一个空白模型。金宝app要保存模型，请选择文件>另存为.
To open the Simulink Library Browser and then open theHDL编码器块库，选择Library Browserbutton in the Simulink Editor. Alternatively, at the command line, enter
```
slLibraryBrowser
```
要过滤Simulink库浏览金宝app器以显示支持HDL代码生成的块库，请使用金宝apphdllib功能:
```
hdllib
```

HDL编码器模型模板

Complex Multiplier

The Complex Multiplier template shows how to model a complex multiplier-accumulator and manually pipeline the intermediate stages. The hardware implementation of complex multiplication uses four multipliers and two adders.

该模板应用以下最佳实践：

在里面Configuration Parameters dialog box, inHDL Code Generation>全局设置,Reset type设定为同步.
为了提高速度，Delay将磁带映射到硬件中的寄存器，位于乘数和加法器的输入和输出处。
To support the output data of a full-precision complex multiplier, the output data word length is manually specified to be (operand_word_length* 2) + 1.
例如，在模板中，操作数字长度为18，输出单词长度为37。

MATLABArithmetic

The MATLAB Arithmetic template contains MATLAB arithmetic operations that infer DSP48s in hardware.

例如，ml_mul_accMATLAB功能block shows how to write a multiply-accumulate operation in MATLAB.HDLFIMATH应用HDL代码生成的定点数学设置。

功能Y = FCN（U1，U2）% design of a 6x6 multipler% same reset on inputs and outputs% followed by an addernt = numerictype（0,6,0）;nt2 = numerictype（0,12,0）;fm = hdlfimath;persistentu1_reg u2_reg mul_reg add_reg;ifisempty(u1_reg) u1_reg = fi(0, nt, fm); u2_reg = fi(0, nt, fm); mul_reg = fi(0, nt2, fm); add_reg = fi(0, nt2, fm);endmul = mul_reg; mul_reg = u1_reg * u2_reg; add = add_reg; add_reg(:) = mul+add; u1_reg = u1; u2_reg = u2; y = add;

只读存储器

The ROM template is a design pattern that maps to a ROM in hardware.

该模板应用以下最佳实践：

At the output of the lookup table, there is a Delay block withResetType=none.
The lookup table is structured such that the spacing between breakpoints is a power of two.
使用具有两个功率的表尺寸使HDL编码器能够生成移动操作而不是除法操作。如有必要，请用零放置桌子。
The number of lookup table entries is a power of two. For some synthesis tools, a lookup table that has a power-of-two number of entries maps better to ROM. If necessary, pad the table with zeros.

Register

寄存器模板显示了如何建模硬件寄存器：

在Simulink, using the Delay block.
在MATLAB, using persistent variables.
This design pattern also shows how to usecast自动传播数据类型。

The MATLAB code in theMATLAB功能block uses a persistent variable to model the register.

功能y = fcn(u)％单位延迟实现，该实施将映射到硬件中的寄存器persistentu_d;ifisempty（u_d）% defines initial value driven by unit delay at time step 0u_d = cast(0,'like', u);end% return delayed input from last sample time hity = u_d;% store the current inputu_d = u;

SRL

SRL模板显示了如何实现硬件中映射到SRL16的移位寄存器。您可以使用类似的模式将其映射到SRL32。

在里面shift register subsystem, the轻拍延迟implements the shift operation, and theMATLAB功能,select_tap, implements the output mux.

在select_tap, the zero-based address,addr增加1个，因为MATLAB索引是一个基于一个基于一个的。

功能dout = fcn(addr, tdelay) %#codegen addr1 = fi(addr+1,0,5,0); dout = tdelay(addr1);

在生成的代码中，HDL编码器自动省略了增量，因为Verilog^®and VHDL^®are zero-based.

该模板还适用以下最佳实践，用于映射到硬件中的SRL16：

For the轻拍延迟block:
- 在“块参数”对话框中，在clude current input in output vector未启用。
- 在“ HDL块属性”对话框中，ResetType设定为none.
For theSubsystemblock, in the HDL Block Properties dialog box,FlattenHierarchy设定为在.