处理器,the-Loop Simulation

Test generated code on target processor or simulator

A processor-in-the-loop (PIL) simulation cross-compiles generated source code, and then downloads and runs object code on your target hardware. By comparing normal and PIL simulation results, you can test the numerical equivalence of your model and the generated code. During a PIL simulation, you can collect code coverage and execution-time metrics for the generated code.

A PIL simulation requires a target connectivity configuration.

Objects

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Target Connectivity

`rtw.connectivity.ComponentArgs`	Provide parameters for each target connectivity component
`rtw.connectivity.Config`	Define connectivity implementation that comprises builder, launcher, and communicator components
`rtw.connectivity.ConfigRegistry`	Register connectivity configuration
`rtw.connectivity.MakefileBuilder`	Configure toolchain-based build process
`rtw.connectivity.Launcher`	Control downloading, starting, and resetting of a target application
`rtw.connectivity.RtIOStreamHostCommunicator`	Configure development computer communications with target processor
`rtw.pil.RtIOStreamApplicationFramework`	Configure target-side communications

Functions

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rtIOStream API

`rtIOStreamClose`	Shut down communications channel
`rtIOStreamOpen`	Initialize communications channel
`rtIOStreamRecv`	Receive data through communication channel
`rtIOStreamSend`	Send data through communication channel

Connectivity Testing

`rtiostreamtest`	Test custom rtiostream interface implementation
`rtiostream_wrapper`	Test rtiostream shared library functions in MATLAB
`piltest`	Verify custom target connectivity configuration for Simulink PIL simulation

Apps

SIL/PIL Manager

Verify generated code

Topics

SIL and PIL Simulations

An overview of software-in-the-loop (SIL) and processor-in-the-loop simulations (PIL).

Choose a SIL or PIL Approach

Test code generated from top models, referenced models, or subsystems.

Create PIL Target Connectivity Configuration for Simulink

Customize PIL simulation for your target environment.

Host-Target Communication for Simulink PIL simulation

Use thertiostreamAPI for communication between your development computer and target hardware during a PIL simulation.

Specify Hardware Timer

使用代码Replacemen指定一个硬件定时器t Tool.

Configure and Run PIL Simulation

Set up and run top-model PIL, Model block PIL, and PIL block simulations.

SIL/PIL Manager Verification Workflow

A simplified workflow for verifying generated code.

PIL Simulation Sequence

How a PIL simulation proceeds.

Simulation Mode Override Behavior in Model Reference Hierarchy

How the simulation mode of the top model or parent model determines the simulation behavior of a model hierarchy.

Field-Oriented Control of Permanent Magnet Synchronous Machine

Simulate motor control system, generate controller code, and use PIL simulation to test numerical equivalence and profile code execution times.

SIL and PIL Limitations

Modeling and code generation features that are not supported or partially supported by SIL and PIL simulations.

Troubleshooting

View SIL and PIL Files in Code Generation Report

Produce a code generation report and static code metrics that cover SIL and PIL files.

Verification of Code Generation Assumptions

The SIL or PIL simulation checks code generation assumptions.

Featured Examples

Test Generated Code with SIL and PIL Simulations

Use software-in-the-loop (SIL) and processor-in-the-loop (PIL) simulations to test numerical equivalence between model components and generated code.

Open Script

Configure Processor-In-The-Loop (PIL) for a Custom Target

Create target connectivity configuration and run PIL simulation.

Open Live Script

Create a Target Communication Channel for Processor-In-The-Loop (PIL) Simulation

Usertiostreaminterface to provide a communication channel for PIL simulations.