Clock Rate Pipelining

This section contains parameters in theHDL Code Generation>Optimization>Pipeliningtab of the Configuration Parameters dialog box. Using the parameters in this section, you can improve the timing of your design on the target device. Enable clock-rate pipelining and allow clock-rate pipelining at the DUT output ports to run the pipeline registers at a faster clock rate on the target FPGA device.

Clock-rate pipelining

If your design contains multicycle paths, use clock-rate pipelining to insert pipeline registers at a clock rate that is faster than the data rate. This optimization improves the clock frequency and reduces the area usage without introducing additional latency. Clock-rate pipelining does not affect existing design delays in your model. It is an alternative to using multicycle path constraints with your synthesis tool.

Settings

Default:On

On: Insert pipeline registers at the clock rate for multi-cycle paths.
Off: Insert pipeline registers at the data rate for multi-cycle paths.

Dependency

If you specify anOversampling factorgreater than one, make sure that you select theClock-rate pipeliningcheck box. Clock-rate pipelining identifies regions in your model that run at the same slow data rate and are delimited byDelayblocks or blocks that introduce a rate transition. The code generator converts these regions to the faster clock rate by introducing重复blocks at the input of the region andRate Transitionblocks at the output of the region.

Command-Line Information

Property:ClockRatePipelining

Type:character vector

Value:'on'|'off'

Default:'on'

To set this property, usehdlset_paramormakehdl. To view the property value, usehdlget_param.

For example, you can use theClockRatePipeliningsetting when you generate HDL code for thesymmetric_firsubsystem inside thesfir_fixedmodel using either of these methods.

Pass the property as an argument to themakehdlfunction.

makehdl('sfir_fixed/symmetric_fir', ... 'ClockRatePipelining','on')

When you usehdlset_param, you can set the parameter on the model and then generate HDL code usingmakehdl.
```
hdlset_param(“sfir_fixed”、“时钟RatePipelining','on') makehdl('sfir_fixed/symmetric_fir')
```

Allow clock-rate pipelining of DUT output ports

For DUT output ports, insert pipeline registers at the clock rate instead of the data rate.

Settings

Default:Off

On: At DUT output ports, insert pipeline registers at clock rate.
Off: At DUT output ports, insert pipeline registers at data rate.

Dependency

When you specify this parameter, make sure that you select theClock-rate pipeliningcheck box.

Command-Line Information

Property:ClockRatePipelineOutputPorts

Type:character vector

Value:'on'|'off'

Default:'off'

To set this property, usehdlset_paramormakehdl. To view the property value, usehdlget_param.

For example, you can use theClockRatePipelineOutputPortssetting when you generate HDL code for thesymmetric_firsubsystem inside thesfir_fixedmodel using either of these methods.

Pass the property as an argument to themakehdlfunction.

makehdl('sfir_fixed/symmetric_fir', ... 'ClockRatePipelineOutputPorts','on')

When you usehdlset_param, you can set the parameter on the model and then generate HDL code usingmakehdl.

hdlset_param(“sfir_fixed”、“时钟RatePipelineOutputPorts','on') makehdl('sfir_fixed/symmetric_fir')