主要内容

Zero-Order Hold

Implement zero-order hold sample period

  • 库:
  • 金宝appSimulink /离散

    HDL Coder / Discrete

  • Zero-Order Hold block

描述

TheZero-Order HoldBlock在您指定的示例期内保存其输入。如果输入是向量,则该块将在同一样本周期内保存向量的所有元素。

You specify the time between samples with theSample timeparameter. A setting of-1指块继承Sample time

Tip

请勿使用零级保持块来创建以不同的样本速率运行的块之间的快速降低过渡。而是使用Rate Transitionblock.

巴士支持金宝app

The Zero-Order Hold block is a bus-capable block. The input can be a virtual or nonvirtual bus signal. No block-specific restrictions exist. All signals in a nonvirtual bus input to a Zero-Order Hold block must have the same sample time, even if the elements of the associated bus object specify inherited sample times. You can use aRate Transitionblock to change the sample time of an individual signal, or of all signals in a bus. SeeModify Sample Times for Nonvirtual Buses具有公共汽车的块for more information.

You can use an array of buses as an input signal to a Zero-Order Hold block. For details about defining and using an array of buses, see将公交车结合成一系列公共汽车

Comparison with Similar Blocks

The内存,单位延迟, 和Zero-Order Holdblocks provide similar functionality but have different capabilities. Also, the purpose of each block is different.

该表显示了每个块的建议使用。

堵塞 块的目的 Reference Examples
单位延迟 Implement a delay using a discrete sample time that you specify. The block accepts and outputs signals with a discrete sample time.
内存 Implement a delay by one major integration time step. Ideally, the block accepts continuous (or fixed in minor time step) signals and outputs a signal that is fixed in minor time step.
Zero-Order Hold Convert an input signal with a continuous sample time to an output signal with a discrete sample time.

Each block has the following capabilities.

Capability 内存 单位延迟 Zero-Order Hold
Specification of initial condition Yes Yes 不, because the block output at time t = 0 must match the input value.
Specification of sample time 不, because the block can only inherit sample time from the driving block or the solver used for the entire model. Yes Yes
Support for frame-based signals Yes Yes
Support for state logging Yes

端口

输入

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输入signal that the block holds by one sample period.

Data Types:single|double|int8|INT16|INT32|int64|uint8|UINT16|uint32|uint64|Boolean|固定点|枚举|bus

Output

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Output signal that is the input held by one sample period.

Data Types:single|double|int8|INT16|INT32|int64|uint8|UINT16|uint32|uint64|Boolean|固定点|枚举|bus

Parameters

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指定样本之间的时间间隔。要继承样本时间,请将此参数设置为-1。看Specify Sample Time在在线文档中以获取更多信息。

不要指定连续的样品时间0或者[0,0]。This block supports only discrete sample times. When this parameter is-1, the inherited sample time must be discrete and not continuous.

块特征

Data Types

Boolean|bus|double|枚举|固定点|整数|single

直接进料

yes

Multidimensional Signals

Variable-Size Signals

Zero-Crossing Detection

Extended Capabilities

PLC Code Generation
使用Simulink®PLCCoder™生成结构化文本代码。金宝app

Fixed-Point Conversion
使用定点Designer™设计和模拟定点系统。

在R2006a之前引入