Deployment

Create bitstream containing user programming and download it to the FPGA hardware.

To program the FPGA and run your algorithm on the hardware, HDL Coder™ can generate an IP core, and deploy it to the Xilinx^®FPGA boards. You can also program the FPGA board by using the FPGA Turnkey workflow, which generates HDL code for your algorithm and the FPGA top level wrapper and then deploys your design to the board.

Topics

IP Core Generation

IP Core Generation Workflow for Xilinx FPGA Boards

Learn how to use the IP Core Generation workflow with standalone FPGA devices and embed the IP core into the reference design.

Default System Reference Design

设计一个学习系统默认引用d using the reference design.

FPGA Turnkey

Program Standalone Xilinx FPGA Development Board from Simulink

This example shows how to target a Xilinx FPGA development board for synthesis using the FPGA Turnkey workflow.

Program Standalone Xilinx FPGA Development Board from MATLAB

FPGA Turnkey workflow for deployment to standalone FPGA hardware

Featured Examples

IP Core Generation Workflow without an Embedded ARM Processor: Xilinx Kintex-7 KC705

Use the HDL Coder™ IP Core Generation Workflow to develop reference designs for Xilinx® parts without an embedded ARM® processor present, but which still utilize the HDL Coder™ generated AXI interface to control the DUT. This example will use MATLAB as AXI Master IP from HDL Verifier™ and Xilinx JTAG Master to access the HDL Coder™ generated DUT registers. For the MATLAB as AXI Master, you can access DUT registers from MATLAB directly. For the Xilinx JTAG Master, you can access the DUT registers using Vivado Tcl Console by writing Tcl commands. The FPGA design is implemented on the Xilinx Kintex-7 KC705 board.

Open Script

IP Core Generation Workflow with a MicroBlaze processor: Xilinx Kintex-7 KC705

Use the HDL Coder™ IP Core Generation Workflow to develop reference designs for Xilinx® parts without an embedded ARM® processor present, but which still utilize the HDL Coder™ generated AXI interface to control the DUT. Specifically, this example will use the Xilinx Kintex-7 KC705 board and a MicroBlaze™ soft processor running a LightWeightIP (lwIP) based TCP/IP firmware server in the reference design to access the HDL Coder™ generated DUT registers from anywhere on the connected network. Further, this example will also highlight the difference between accessing data from a collection of registers implemented as multiple scalar ports and a collection of registers implemented as a single vector port.