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Generate Black Box Interface for Referenced Model

When to Generate a Black Box Interface

Specify a black box implementation for the Model block when you already have legacy or manually-written HDL code. HDL Coder™ generates the HDL code that is required to interface to the referenced HDL code.

Code is generated with the following assumptions:

  • Every HDL entity or module requires clock, clock enable, and reset ports. Therefore, these ports are defined for each generated entity or module.

  • Use of Simulink®data types is assumed. For VHDL®code, port data types are assumed to beSTD_LOGICorSTD_LOGIC_VECTOR.

If you want to generate code for a multirate, multiclock DUT that includes a referenced model, seeModel Referencing for HDL Code Generation.

How to Generate a Black Box Interface

To instantiate an HDL wrapper, or black box interface, for a referenced model:

  1. 右键单击模型块和选择HDL Code>HDL Block Properties.

    In the HDL Block Properties dialog box:

  2. Generate HDL code for your DUT subsystem.

Caveats and Limitations

  • If you run thecheckhdlfunction to check the compatibility of your model for HDL code generation, the function does not check the port data types within the referenced model.

  • If you encounter typing or naming conflicts between vector ports when interfacing two or more generated VHDL code modules, use theScalarizePortsproperty to generate nonconflicting port definitions. For more information, seeScalarize ports.

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