Increment Stored Integer

增加存储整数值的信号

expand all in page

Libraries:
Simulink / Additional Math & Discrete / Additional Math: Increment - Decrement
高密度脂蛋白Coder / Math Operations

Description

TheIncrement Stored Integerblock increases the stored integer value of a signal by one.

Floating-point signals also increase by one, and overflows always wrap.

Examples

Increment and Decrement Stored Integer Values

Increase and decrease the stored integer value of a signal by one.

Open Model

Ports

Input

expand all

Port_1—Input signal
scalar | vector | matrix

Input signal, specified as a scalar, vector, or matrix.

Output

expand all

Port_1—Output signal
scalar | vector | matrix

Output is the stored integer value of the input signal increased by one. Floating-point signals also increase by one, and overflows always wrap. The output has the same data type and dimensions as the input.

Block Characteristics

Data Types	`double`\|`fixed point`\|`integer`\|`single`
Direct Feedthrough	`yes`
Multidimensional Signals	`yes`
Variable-Size Signals	`yes`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

The code generator does not explicitly group primitive blocks that constitute a nonatomic masked subsystem block in the generated code. This flexibility allows for more efficient code generation. In certain cases, you can achieve grouping by configuring the masked subsystem block to execute as an atomic unit by selecting theTreat as atomic unitoption.

高密度脂蛋白Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

高密度脂蛋白Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

高密度脂蛋白Architecture

This block has one default HDL architecture.

高密度脂蛋白Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is`0`. For more details, seeConstrainedOutputPipeline(HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeInputPipeline(HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeOutputPipeline(HDL Coder).

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a

Increment Stored Integer

Description

Examples

Increment and Decrement Stored Integer Values

Ports

Input

Port_1—Input signal
scalar | vector | matrix

Output

Port_1—Output signal
scalar | vector | matrix

Block Characteristics

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

高密度脂蛋白Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Topics

Increment Stored Integer

Description

Examples

Increment and Decrement Stored Integer Values

Ports

Input

Port_1—Input signalscalar | vector | matrix

Output

Port_1—Output signalscalar | vector | matrix

Block Characteristics

Extended Capabilities

C/C++ Code GenerationGenerate C and C++ code using Simulink® Coder™.

高密度脂蛋白Code GenerationGenerate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point ConversionDesign and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Topics

Port_1—Input signal
scalar | vector | matrix

Port_1—Output signal
scalar | vector | matrix

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

高密度脂蛋白Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.