Model Info

Display model properties and text in model

expand all in page

Libraries:
Simulink / Model-Wide Utilities
HDL Coder / Model-Wide Utilities

Description

TheModel Infoblock displays model properties and text about a model on the mask of the block. Use theModel Infoblock dialog box to specify the content and format of the text that the block displays. You can select model properties to display on the block. In the text displayed on the block mask, Simulink^®replaces the property name with the current value of the property in the model.

Examples

Simulating Systems with Variable Transport Delay Phenomena

Two cases where you can use Simulink® to model variable transport delay phenomena.

Open Model

Parameters

expand all

Specify Text and Properties to Display—Content and format of the text to display
no default

Use theEnter text and tokens to display on Model Info blockedit box to specify the text and properties to display.

In the edit box, enter any text you want to display on the block mask. Edit the default textModel Info.
To display a model property on the block mask, select a property in theModel propertieslist and click the right arrow button.
The block adds a token of the form%to the edit box. In the text the block mask displays, Simulink replaces the token with the value of the property.
1. For example, if you selectDescriptionin theModel propertieslist and click the right arrow button, then the token
```
%
```
  appears in the right edit box.
2. You could add some explanatory text before the model property, e.g. “Model description:”.
3. When you clickApplyorOK, Simulink displays your new text and the current value of the model property on the block mask in the Model Editor.
SeeAccess Model Information Programmatically为描述模型的属性。

If you are interested in source control information, for a flexible interface to source control tools, use a project. SeeSource Control in Projects.

Block Characteristics

Data Types
Direct Feedthrough	`no`
Multidimensional Signals	`no`
Variable-Size Signals	`no`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

TheModel Infoblock is ignored during code generation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

高密度脂蛋白编码器™也提供了额外的配置ns that affect HDL implementation and synthesized logic.

Best Practices

When usingModel Infoblocks in models targeted for HDL code generation, consider using only ASCII characters in the text that you enter to display on theModel Infoblock. If you have non-ASCII characters in the generated HDL code, RTL simulation and synthesis tools can fail to compile the code.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is`0`. For more details, seeConstrainedOutputPipeline(HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeInputPipeline(HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeOutputPipeline(HDL Coder).

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Version History

Introduced before R2006a

Model Info

Description

Examples

Simulating Systems with Variable Transport Delay Phenomena

Parameters

Specify Text and Properties to Display—Content and format of the text to display
no default

Block Characteristics

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Version History

See Also

Topics

Model Info

Description

Examples

Simulating Systems with Variable Transport Delay Phenomena

Parameters

Specify Text and Properties to Display—Content and format of the text to displayno default

Block Characteristics

Extended Capabilities

C/C++ Code GenerationGenerate C and C++ code using Simulink® Coder™.

HDL Code GenerationGenerate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code GenerationGenerate Structured Text code using Simulink® PLC Coder™.

Version History

See Also

Topics

Specify Text and Properties to Display—Content and format of the text to display
no default

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.